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ProcSoC systems



Gidel's ProcSoC3 & ProcSoC10 System Targets ASIC/ SoC Development Projects of 6 to 360+Million Gates

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patented connectivity of Gidel's SoC prototyping systems


 

Overview

As a module of the ProcSoC™ Verification System the ProcSoC10™ provides scalability for multiple systems to be interconnected and used to verify SoC designs with 360 million+ gates. Gidel's ProcSoC10 is itself a modular and scalable ASIC verification system.

The ProcSoC10 module has a rated capacity of up to 120 million ASIC gates.  Fast /Gigabit Ethernet communication combined with Gidel's development tools, enable users to run regression tests on their ASIC designs and to debug the entire chip design including embedded software across their company's local area network. The ProcSoC10 is operated in an in-circuit emulation mode with high performance I/O’s interfaced to a target or prototype system. Real world data and applications software comprise test suites with the system’s debugging tools providing visibility to buses and internal nodes of the design.

Up to ten, 6 million/ 12 million gate, reconfigurable Proc6M / Proc12M boards, each with two, interconnected high speed
Stratix IV 8200 FPGAs or Stratix III 340 FPGAs, may be in a single ProcSoC10 system. Each ProcSoC10 module can perform as a single ASIC device at typical system speeds of 35 to 300MHz, or shared to verify different design blocks or small, independent SoC designs.

The ProcSoC10’s unique interconnect topology, enables any FPGA to directly connect to any other FPGA in the same ProcSoC10 or other ProcSoC10s, through up to six interconnections per FPGA of 118 pins each. Additionally there are 261 FPGA-to-FPGA I/O connections on each Proc6M/ Proc12M element and 5 global lines connecting all FPGAs.

The system is optimized for speed, eliminating the extra delays inherent within routing switches, and hops through FPGAs and other connection technologies used in legacy systems.

Fast, efficient implementation and debug shortens your project schedules.

Every ProcSoC10 module includes the Proc Developer’s Kit. The Kit consists of a suite of tools for the efficient mapping of your chip designs into ProcSoC10 systems, and for debugging your design. The ProcWizard™ Software manages these processes and integrates the files generated by best-of-breed tools for partitioning, design mapping, synthesis and place and route. The ProcWizard also generates a unique application driver. For each user's application, it will generate a dedicated driver which is extremely easy to use with optimized performance. This enables fast setup to run comprehensive test benches from a host across a network to the verification system.

The Proc Developer's Kit includes the following:

(1) The ProcWizard Software for configuring and debugging ASIC and ASSP designs in the verification system,

(2) ProcMultiPort, ProcMegaFIFO, and ProcMegaDelay IPs, for configuring onboard memory and automatic generation of
     DMA controllers for fast data transfers between the verification hardware and software on the host computer,

(3) ProcHILs enabling higher level of test-bench design using Simulink, plus

(4) Altera’s Quartus II Software suite for FPGA mapping, synthesis, and place and route of designs into the verification hardware,

(5) Altera’s Ethernet blaster enabling remote access to SignalTap.

Each memory block can have up to 16 ports, each with their own clock domain and data width. ProcMegaFIFO IP provides a fast efficient mechanism to transfer data to/from the ProcSoC10 user design and a host computer, or between sub-designs within the ProcSoC10 using on board memory as a large FIFO. ProcMegaDelay IP provides a simple mechanism for using on-board memory for large delays used for frame and field delay 3D matrix computation and more.  

This entire reusable system enables you to focus on your proprietary value-added design, and not spend your valuable months of effort to create verification platforms that are unique to a specific project.

ProcSoC3 system offers the same features as the ProcSoC10 but for smaller application requires 3 to 36 million ASIC gates.

To download the Product Brief, please click here

   

Benefits

  • Leading edge performance.
  • Maximum flexibility to fit customer needs.
  • Cuts development cycle time and budget.
  • Reliability.
  • Maintainability.
  • Long life cycle.
     
  • Find and Resolve More Bugs Faster.

    With the ProcSoC10, your tests will run faster, and you will find those hard to reach bugs quicker. The Proc Developer’s Kit contains robust debug capabilities allowing use of both distributed memories within the FPGAs and onboard memories to capture signal data.  The ProcWizard debug GUI enables direct access to the design IOs and running of tests.  Scripts are automatically generated of the testing process for replay. The configurable multi-port on-board memories can be easily set up to capture data from thousands of probe points during testing with virtually unlimited depth. Also, with the Altera's SignalTap or Synplicity's Identify probes can be set for more visibility using internal FPGA memories. This combination of internal and external memory usage for data capture practically eliminates the need to recompile the FPGAs for visibility.

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    Proc Boards: ProceV |ProcStarIV | ProceIV | Proc104 | ProcStarIII  | ProceIII 
    ProcWizard | ProcMultiPort | Proc Boards | Proc Daughterboards | ProcHILs | ProcFG

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