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ProceV
 
Gidel's ProceV is an ALTERA Stratix V GX/GS , PCIe Gen. 3  based Board

Overview

 

The ProceV™ system is based on Altera’s newest generation Stratix V FPGA device. The ProceV provides massive capacity (up to 952K LEs), and high memory and I/O performance. In addition to 8-Lane PCIe gen 3, twenty six 12.5/14.1 Gb/s transceivers provide external IOs of up to 366 Gb/s (full duplex). The combination of high-speed direct communication to the FPGA via PCIe, CXP, SFP+, and General Purpose high-speed transceivers makes the ProceV ideal for low-latency, high performance networking and HPC applications. Powerful memory scheme, composed of embedded memory with 8 TB/s throughput, 16 GB ECC DDR III and optional 288 Mb DDR II SRAM, enables high bandwidth computation and networking, and unique flexibility to achieve diverse algorithm architectures. Using an external clock, a Gidel or user dedicated add-on daughter boards, the FPGA device can directly interface with standard protocols such as HDMI, SDI and Camera Link as well as with user's propriety IO systems. Eight-lane PCIe Gen. 3 interface allows for strong co-processing between a standard PC operating system and an FPGA based accelerator.  

The ProceV system, with Gidel's ProcDeveloper's Kit and tools, offers incredible performance yet supports quick implementation of your unique design. These unique features are achieved by eliminating the need for a high-speed board design, a PCI Express application driver, board constraints and environment FPGA code. The generated HDL code enables high throughput, easy-to-use parallel access to large memories. As a result, designers can focus on their proprietary value-added design. User designs may be in HDL, C-based, Simulink (graphical design) or any combination of them.



Key Features

·   Stratix V GX (A3, A7, AB)/GS (D5, D8) FPGAs

·   8-lane PCI Express Gen3 (PCIe x8) host interface

·   Dynamically reconfigurable FPGA

·   Reconfigurable transceivers supporting multiple protocols and data rates

·   Up to 3,926 18×18 Variable Precision Multipliers

·   1 CXP connector cage suitable for 100 Gigabit Ethernet (100GBASE-CR10, 100GBASE-SR10), 3×40 Gigabit Ethernet, or single Infiniband 12×QDR link

·   2 SFP+ cage suitable for 10 Gigabit Ethernet and Optical Transport Network

·   RJ45 port suitable for 1000MBase-T and 100MBase-TX

·   2× High-Speed Inter-Board connectors (up to 12×14.1Gb/s full duplex GPIO) for board to board and proprietary daughterboards connectivity

·   12 general purpose LVTTL External IOs

·   External clock input via an SMA connector

·   Four level memory structure (16+ GB).

Typical sustain throughput of 8000 GB/s for internal memories and 25+ GB/s for on-board memory as follows:

·        Up to 2640 M20K (20K-bit) SRAM blocks (52 Mb) with a typical throughput of 8,000 GB/s at 300 MHz

·        Up to 17,960 Enhanced MLAB (640-bit) SRAM blocks (8 Mb)         

·        2 ×DDR3 ECC SODIMMs Banks with up to a total of 16 GB at a maximum sustain throughput of 19.2 GB/s  

·      Optional: 2× 144Mb SRAM memories (up to 400Mhz) at a sustain throughput of 6.4 GB/s

·   Support for a single PSDB1™ type daughter board used for a Gidel's off-the-shelf or user add-on Interface

·   Stand-alone mode

·   Typical system frequencies: 150-450 MHz

·   Flexible clocking system

·   Volatile and non-volatile design security

·   Supported by Gidel's Proc Developer's Kit

Benefits
 
  • Leading edge performance.

  • Advance development tools.

  • Low power consumption.

  • Reliability.

  • Maintainability.

  • Long life cycle.


    Target Applications

    • Trading

    • Life science Applications

    • ASIC and SoC Prototyping

    • DSP (Digital Signal Processing) and HPRC (High Performance Reconfigurable Computing)

    • High-speed low latency networking and network analysis

    • Surveillance, Machine Vision and Imaging

    • High performance acquisition systems

    • Complex algorithm and IPs validation

    Operating systems

  • Microsoft Windows.
  • Linux.



  • Re-Configuration

    • ProceV boards can be easily re-configured by user's software. The re-configuration is accomplished simply by closing the current class object and opening a new application driver object. The board can alternatively be re-configured by calling the Load_IC method or using the ProcWizard development tool in order to merely replace a specific device.

    • The application drivers are automatically generated by ProcWizard.
    • The rapid parallel access DDR III memories can also be reconfigured using the Proc Multiport controller.

     



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