- Open FPGA Frame Grabber and Image Processing
The ProcFG™ ™
is a programmable image acquisition and processing system, based on Gidel’s powerful FPGA Proc™ boards. It provides a flexible acquisition path allowing adding processing functions designed by the user or based on Gidel’s Image Processing Library (GIL), or alternatively, interfacing with third-party imaging libraries.
Selective choice of a Gidel FPGA Proc Board (PCIe up to x8 gen 3) and Gidel daughterboards combined with open source FPGA code provides tremendous flexibility for system integration and for achieving desired system performance.
Gidel's ProcFG combines high-speed acquisition, powerful FPGA processing with selective on-the-fly ROI offloading for convenient processing on standard PC. The ProcFG may capture all incoming image data or dynamically target and extract ROIs based on real-time FPGA analysis of the incoming data.
Gidel's ProcFG supports acquisition from both Line and Area Scan cameras. Line camera’s image strip is partitioned into frames that may be overlapped. Frame overlapping enables localized filtering to process each pixel using neighboring pixels within its own frame.
In addition, the frames may be captured according to reference or global coordinates enabling alignment between captured image and, for example, reference image even when image shift, stretching and/or rotation exist.
Gidel’s ProcWizard generates user’s API for software direct access to GIL and user’s IPs in the FPGA.
Supports Camera Link Base, Medium, Full and 80-bit configurations.
Supports CoaXPress protocol, including Raw, Mono, Planar, Planar Raw, Bayer, RGB, RGBA, YUV, YCbCr601 and YCbCr709 image formats.
Up to 2 × 850MB/s at full-speed acquisition and algorithm processing.
Flexibility to meet camera(s) and processing needs by selecting a fitting combination of Gidel Proc Board and Daughter Boards(s).
Open architecture allowing integration of:
1. User algorithm in FPGA supported by auto-generated API addition.
2. Mixed imaging protocols.
3. Combination of image acquisition and image transmission.
Dynamic configuration of CoaXPress and Camera Link parameters (zones, parallel pixels, zone order direction).
1. Conventional grabbing modes (preset scheme).
2. Selective ROI grabbing using on-the-fly requests from user application.
Automatic partitioning of line scan (and large Area scan) camera input into frames, with a frame overlapping option.
Frames may be grabbed in reference to global coordinates enabling easy comparison with reference image.
Supported by Gidel’s Imaging Library (GIL)
The GIL suite includes an embedded pattern generator
For algorithm development, user's images may be streamed to the ProcFG from Gidel’s ProcCamSim™,
a configurable camera and machine simulator.
The ProcCamSim’s API enables to generate images in real-time.
The ProcCamSim’s open FPGA design allows interfacing
with external IOs such as encoders to achieve
full system simulation stimulus.
Vision algorithm development
Image processing application testing
Vision system reliability testing
Debug of “rarely-appearing” bugs
Proc Boards Supported
ProceV: PCIe gen. 3, single Stratix V FPGA device, support for single daughterboard, up to 16 GB on-board memory.
ProceIII / ProceIV: Single Stratix III or IV FPGA device, support for two daughterboard, up to 8.5 GB on-board memory.
ProcStarIV: up to 4 Stratix III or IV FPGA devices, support for five daughterboard, up to 34 GB on-board memory.
Proc104: PCI/104-Express, single Stratix III or IV FPGA device, support for single daughter-board, up to 8.5 GB on-board memory.
To download the full ProcFG